libisal (2.31.0-0.1) [PTS] [DDPO]

NEW: VCS has unreleased changes: 2.31.0-1 > 2.31.0-0.1

Git: https://salsa.debian.org/openstack-team/third-party/libisal.git
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Branch: debian/caracal
Path: debian/changelog
Repo size: 557056
Browser: https://salsa.debian.org/openstack-team/third-party/libisal
Last scan: 2024-04-26 02:09:09+00
Next scan: 2024-05-04 19:28:00+00
Merge requests: 1

Debian changelog in Git:

libisal (2.31.0-1) UNRELEASED; urgency=medium

  * Remove myself from Uploaders.

 -- Ondřej Nový <onovy@debian.org>  Mon, 18 Mar 2024 16:09:14 +0100

This branch is 4 commits ahead of tag v2.31.0

Git log:

commit fbc9ca2ecdefe82e505995cecaa4a3034293af19
Author: Ondřej Nový <onovy@debian.org>
Date:   Thu Mar 28 12:56:40 2024 +0100

    Sync git with Debian archive

commit dc8374076768b13695db8af7f1c6fc0f8abc0199
Merge: 6b77929 bd22637
Author: Ondřej Nový <onovy@debian.org>
Date:   Thu Mar 28 12:54:51 2024 +0100

    Merge tag 'v2.31.0' into debian/caracal
    
    ISA-L version 2.31.0

commit 6b77929a2e8c7863e06c38897e0c64c209224722
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 18 16:09:14 2024 +0100

    Remove myself from Uploaders

commit 9f1a135abccb4f48f072b7185a8fa8fded7a47c7
Author: Thomas Goirand <zigo@debian.org>
Date:   Thu Jun 2 17:12:52 2022 +0200

    FTBFS on big-endian architectures

commit 7a376694fe01b0d725cf33ca97f9e4a5d11151f5
Author: Ondřej Nový <onovy@debian.org>
Date:   Thu Oct 28 22:46:40 2021 +0200

    releasing package libisal version 2.30.0-4

commit f3f988334111d2308ae2ca36d9646901d592e1bf
Author: Ondřej Nový <onovy@debian.org>
Date:   Thu Oct 28 22:46:33 2021 +0200

    Bump standards version to 4.6.0.

commit f7b264a399149bfc37582838c887af3c9597e183
Author: Ondřej Nový <onovy@debian.org>
Date:   Thu Oct 28 22:43:28 2021 +0200

    Fix symbols file for new architectures.

commit c9b6eedde637c9f086ae13e7e7fb4f7a3432e8d3
Author: Ondřej Nový <onovy@debian.org>
Date:   Thu Oct 28 18:48:34 2021 +0200

    releasing package libisal version 2.30.0-3

commit 20dc7d6c1217e2ca70fa06984abf58da07dcf849
Author: Ondřej Nový <onovy@debian.org>
Date:   Thu Oct 28 18:47:53 2021 +0200

    Build for all architectures.

commit f216637865c6819c72bbe073326593c1dcc69546
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 11:18:13 2020 +0100

    releasing package libisal version 2.30.0-2

commit 3174f419a6e877eff7018f9c4afa521767d63eb1
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 11:17:54 2020 +0100

    Update ARM symbols file.

commit 3bd4afb7b563b7409742ca7ca9602987d2448de8
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 10:32:52 2020 +0100

    releasing package libisal version 2.30.0-1

commit 5df9d8be2338600bd1ee77319db8980c3d775392
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 10:29:50 2020 +0100

    Bump standards version to 4.5.1.

commit c83af5a5a6222d1635c036b3239e985bf75575f1
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 10:29:37 2020 +0100

    Bump debhelper compat level to 13.

commit 7d2666359b9691d9073e631acb8af1a85f88ca68
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 10:27:11 2020 +0100

    Update symbols file.

commit 1dc63279290f7624426f8ad884871985d6080de2
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 10:23:43 2020 +0100

    New upstream release.

commit 5c82c6bad2e1ebffc325d4138dacb945352e2155
Merge: 2988108 2df39cf
Author: Ondřej Nový <onovy@debian.org>
Date:   Tue Dec 1 10:23:34 2020 +0100

    Merge tag '2.30.0' into debian/victoria
    
    ISA-L 2.30 release

commit 2df39cf5f1b9ccaa2973f6ef273857e4dc46f0cf
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Nov 6 18:08:16 2020 -0700

    build: Bump revision to 2.30
    
    Change-Id: If6d696ee76f3949d3cf5aff34403df65bce2c6b9
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 05f6a0bb39c8816e8cd72eca284d8a39ad2c3c84
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Nov 4 12:40:34 2020 -0700

    Update release notes for v2.30 additions
    
    Change-Id: Icbb1faa2b67d8d18b1c7cde9f09774ebd895a6df
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit ece814e912667000624398d05062adb0685adad0
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Oct 30 12:38:13 2020 -0700

    doc: Add details on build and test
    
    Change-Id: I58401ed26ba8a0a7fad0191b4c1bbb461d0311e6
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit dca9dd221eab884d4848e55f355e67d69381fe8e
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Nov 4 12:29:37 2020 -0700

    igzip: Use unaligned load on static header to fix usan
    
    Clang with sanitizer on was catching on cast of static header.
    Switching to uload64 macro for better general solution.
    
    Change-Id: I495d440407bb1773841e2f7cdc48bd95fc1a2df4
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 269df8a67d6c2ef018b045a1993ea4500e1501a9
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Nov 2 19:11:18 2020 -0700

    igzip: Fix order of args check in new dictionary function
    
    In the newly added function isal_deflate_process_dict(), a null check
    was added to the dictionary struct but was ineffectual because of the
    order.
    
    Change-Id: I3b3e70997210794de102b1348e1467295871cee2
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 24a98e3e8751dfefb5250674dc4637962547ddb3
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Oct 28 17:43:53 2020 -0700

    Fix missing files in extra dist
    
    Change-Id: I83e62344fab72afd755453d4eb43e9c236ba2b86
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 79143208acdeb6dba61e609088ad3936c5361ea3
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Oct 28 17:28:43 2020 -0700

    test: Add testing for new dictionary functions
    
    Change-Id: I0b0a151374acfe9b44c7a2be4bb959df59356d97
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 19035917f45fa84ab3c7aeebe8b164b2c389cf26
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Tue Oct 20 09:56:09 2020 -0700

    igzip: Add new functions for faster dictionary compression
    
    Change-Id: Id55728fea286d144f8a11192ab02ccc8503d7b25
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 438ecd8187984e2968f86d312b447474672296f9
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Tue Oct 20 09:56:02 2020 -0700

    Update custom hufftable tool for saving histogram
    
    Change-Id: I515217b19373b8f996ff887268862cf2b102f3a4
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 89f7c46cd53a71a31f99aaa3c9aa5776d9b7b8ea
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Tue Oct 20 09:55:53 2020 -0700

    Change igzip_file_perf to accept 0 time
    
    Change-Id: Ie2edf8e742d0bcdd9a008704f997006f8f5009ac
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 9968e7a032212aa66826414cac560e4a4b2a2cc5
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Tue Oct 20 09:55:47 2020 -0700

    Change gen cust hufftables to accept dictionary
    
    Change-Id: I4eed03bdb91030b16b3ecfd8076adc890e4f59a2
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 63dffab948cf8918d085e9cd7c1ab2127acd534e
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Tue Oct 20 09:55:40 2020 -0700

    igzip: Change pre-gen inflate table to multi-symbol
    
    Change-Id: I4b0dac1e5aa2796be17644b893e3b6c7aed05876
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit d7927673ba9908178aecf5d4084ac6e681688d0d
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Tue Oct 20 09:55:24 2020 -0700

    igzip: Inflate detect pre-gen header and use pre-expanded
    
    Performance improvement for inflate to skip the time-consuming process of decode
    table expansion when the header matches a known common dymanic one such as
    produced by level 0 compression.
    
    Change-Id: Ia2550b812a062b7cc2eb1b72bcb609f1a631e40b
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit cc9ed539725b4277d76701415983b83f4e6de3d6
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Thu Aug 27 11:16:30 2020 -0700

    build: Fix nmake check for multiple arch
    
    Change-Id: I36c3616163f6fec61dda9cf8b35ca561e59477c9
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 794b8b60c12933ff45effdf94580de1fb5e62d4e
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Aug 26 11:41:03 2020 -0700

    build: Add test to check for nmake consistency
    
    Change-Id: I1180ba749d54e7ef433b01b33450e52ac5dbb2bb
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 24623b8b8202ed626274a5481fd2619939cec759
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Aug 26 09:49:23 2020 -0700

    crc: Fix missing object omitted from nmake file
    
    Previous new crc version missed the update for nmake.
    
    Change-Id: Ie529ee9d70d8d0ab8a8af3bd2720405802180d1e
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit ec73d39086d78649e0d23c8ade039a41e2ead1ff
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Aug 21 17:15:58 2020 -0700

    crc: Add new vclmul version of crc32_iscsi
    
    Change-Id: I1c509c6ea312b6eb4e1c2c1c8bb7044f7b043e0d
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit ae45f60e780ccc614bb2bd1c4e7116bd10eb70bb
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Jul 6 19:36:19 2020 -0700

    igzip: Add cli feature to inflate concatenated gz files
    
    Change-Id: I2beade6682e78fda30a18228a8660201ae7bf718
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 93049d0d1f712c907863ab785d014e825917ae77
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Jul 8 19:13:33 2020 -0700

    igzip: Fix read header for correct null checking and init
    
    Issue with reading header only appears when combined with new feature in cli of
    multiple concatenated gzip files.
    
    Change-Id: Id8df9150c6f27d8b22e810b511291f3fcf136723
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 2049d8dc816154392868e271e3857666cc704a60
Author: Ruben Vorderman <r.h.p.vorderman@lumc.nl>
Date:   Wed Jul 22 11:26:38 2020 +0200

    Add conda shield to readme
    
    This will make it easier for users to get the latest version. Installing with conda is easier than compiling it yourself. Distro packages (such as Debian's) do not always ship the latest version while conda-forge can. This badge will advertise this install method.
    
    Change-Id: I99a1853a00e55fdf0c574c9906675738ac278121
    Signed-off-by: Ruben Vorderman <r.h.p.vorderman@lumc.nl>

commit 1c71f9c0aec8fdb95ea7b7468591cd46cb111c2f
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Fri Jul 3 18:15:56 2020 +0800

    crc32: tweak performance of crc32/crc32c
    
    Tweak performances with prefetch instructions.
    
    Below is the test results:
    - Neoverse N1: ~30%
    - Cortex-A72: ~3%
    - Cortex-A57: ~90%
    - Others: 50% - 5x
    
    Change-Id: I3ab292a953043dbaea98af3c66778f57da3a1331
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 14e0081bef4032bb232e57e2e646021cdf1d86bd
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Wed Jun 3 02:51:25 2020 +0000

    build: fix build break on non-x86 platform
    
    Arm64 and ppc64 build reports below error:
    "configure: error: conditional "INTEL_CET_ENABLED" was never defined."
    And the error should be report in all non-x86 platform.
    
    Change-Id: I4c1b2fc99091424cfd5c62cf4d6536222b66712d
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 8074e3fe1b9398a9d3b717267790050fc5041594
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri May 22 10:17:59 2020 -0700

    x86: Generate .note.gnu.property section for ELF output
    
    We should generate .note.gnu.property section with x86 assembly codes
    for ELF outputs to mark Intel CET support when Intel CET is enabled
    since all input files must be marked with Intel CET support in order
    for linker to mark output with Intel CET support.  Since nasm and yasm
    can't generate the proper .note.gnu.property section, yasm-cet-filter.sh
    and yasm-filter.sh are added to generate the proper .note.gnu.property
    with linker help.
    
    Verified with
    
    $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
    $ make -j8
    
    on Linux/x86-64.
    
    Change-Id: I14e03a8a9031c8397dc36939a528cf5a827d775a
    Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

commit cd888f01a447dd04c3a8b50362079648d432d2ca
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri May 22 10:46:50 2020 -0700

    x86: Add ENDBR32/ENDBR64 at function entries for Intel CET
    
    To support Intel CET, all indirect branch targets must start with
    ENDBR32/ENDBR64.  Here is a patch to define endbranch and add it to
    function entries in x86 assembly codes which are indirect branch
    targets as discovered by running testsuite on Intel CET machine and
    visual inspection.
    
    Verified with
    
    $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
    $ make -j8
    $ make -j8 check
    
    with both nasm and yasm on both CET and non-CET machines.
    
    Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337
    Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

commit 031450f6977243159dd227c0505cbed0c1666270
Author: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
Date:   Sun Apr 26 13:26:05 2020 +0000

    crc32: Implement default mix mode optimization
    
    Change-Id: Ib3bf04215cca491db522ec33905fe48df173cc2f
    Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>

commit 6c4d3dbf6cb994addf4233c7e8918b94db7fbd65
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Tue Apr 7 16:31:18 2020 +0800

    crc32:NeoverseN1: Change CRC32/PMULL order to PMULL first
    
    To reduce the cache missing events, the mix layout is changed
    to PMULL+CRC. It also relaxes the final delay caused by data
    dependency.
    As results, the cold perf was improved about 20% and warm perf
    was improved about 4%.
    
    Change-Id: I7756f846edcb4f1665b4643a5a0e02283938cfdf
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 92fc8733fabd6be625c57e2ce441fd7851dff38a
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Fri Apr 3 12:31:31 2020 +0800

    crc32: Fix prototype mismatch bug
    
    Change-Id: I7c8a2348441f32a43ff386122612405e418d9947
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 9bcd6768fd907b2172330d4897c8330fb12ea02e
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Fri Apr 3 16:52:47 2020 +0800

    crc32:Adjust hardware folding algorithm flags
    
    Hardware folding algorithm depend on CRC32 and PMULL instruction.
    And it should match both flags .
    
    Change-Id: I361068402db1fe6d7c0bd8d2c7048f1d94880233
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 0033f4218936756441124dde36f2491c6b04c496
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Thu Apr 2 22:05:29 2020 +0800

    crc32:Optimize crc32/c for cortex-a72
    
    Change-Id: Ib1658fd4b87b31d8ea6c93f697b50d9b409c186e
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 5e586843ebcc072c638894b3c099ec617a852fe1
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Mar 30 15:41:31 2020 -0700

    build: Change ms nmake default to nasm and add pdb gen
    
    The nmake default is changed for a modern nasm. Older nasm and yasm versions
    will still work with windows but the nmake options must be changed appropriately
    for max AS_FEATURE_LEVEL to match. Also now generates debug symbol pdb files.
    
    Change-Id: I94a2dd7ecf541c6564ccbd4a184c33995d7b31ad
    Signed-off-by: Poornima Kumar <poornima.kumar@intel.com>
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit a2fc2c000d2dd6872b330554506eafb20bb99561
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Mon Mar 2 13:34:44 2020 +0800

    crc32:Add optimization implementation for Neoverse N1
    
    This patch is base on reference(1) algorithm with some changes.
    - Redefine the block number to two.
      - That's due to only two pipe-line can be used in CRC32 calculate.
    - Redefine the block size:
      - The block size of CRC is 1536B and PMULL is 512B
    - Interleave CRC and PMULL instructions.
    The optimization parameters are calculated base on reference(2)
    
    References:
    - https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
    - https://developer.arm.com/docs/swog309707/a
    
    Change-Id: I1c9e593d59b521f56e4b3c807b396c083c181636
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit f2cf2609cd07c383524d9aecd0a7f668f6b7eafc
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Mon Mar 2 13:09:08 2020 +0800

    multi-binary:Add microarchitecture id reader
    
    This patch provides microarchitecture information
    and make microarchitecture optimization possible. It
    will trap into kernel due to mrs instruction. So it
    should be called only in dispatcher, that will be
    called only once in program lifecycle. And HWCAP must
    be match,That will make sure there are no illegal
    instruction errors.
    
    Change-Id: I393ec742010bf3f10ce335482c0350aa4202c788
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 85f947e1202558926357876166a889c8bf53ccf5
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Tue Mar 17 13:18:56 2020 +0800

    ci: remove unused drone configuration
    
    Change-Id: I20bded8111deb122757dbf259d17cd80010c2bb6
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit af13ed6136c530f44a1047b7e95a06cbb545fb3d
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Mar 20 12:26:30 2020 -0700

    ec: Fix second windows reg push for avx512
    
    Change improper stack push in windows prolog.  Error was not reachable without
    windows nasm support and so went undetected.
    
    Change-Id: I8b715195d1c8efd173843c043d42fc610ddebd17
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit ede04f0a1f4d7ea00cbd13d33c9db35d17575a38
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Mar 16 16:23:55 2020 -0700

    build: Fix for windows to allow nasm use
    
    Previously windows build could only use yasm because some procedural items such
    as proc_start were not supported by nasm.  This adds a few macros and fixes so
    nasm can be used to build on windows.
    
    Change-Id: Ia05dc3ff482f33b0f915bb1be3c7df5e4a753b3a
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 5ab40c79cc2ef7f8dd3ca5fdd1726dee80ff259a
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Tue Mar 17 17:52:06 2020 -0700

    ec: Fix windows reg push for avx512
    
    Push of registers overlapped xmm push.  Error was not reachable without windows
    nasm support and so went undetected.
    
    Change-Id: I0ffd66f6d32ac37ea03fe9b11924968aa50f8fa7
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 472e7011e8f670ace5464c68fc55ae20a24ceea5
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Mar 16 16:12:54 2020 -0700

    ec: Change use of windows macro save_xmm128 to vec
    
    For builds under windows this could emit a non-vec mov that's not optional for
    AVX versions.
    
    Change-Id: I31e6ea3b62d48c5a13f6e83f8d684f0b5551087b
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 7c0ab1d459c2bd43bd900432d721acc4aaf448ad
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Mar 6 17:43:39 2020 -0700

    build: Add auto regenerate of nmake file
    
    Change-Id: Icaa64aa35697c87779df18c3941d3df0f3256546
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 794413ddd24c26852a44ce35e9b87e78c9d4d8b4
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Mar 6 13:45:59 2020 -0700

    ec: Remove arch-specific redundant gf_nvect tests
    
    The gf_{2-6}vect_dot_prod tests were kept in other_tests since the 5,6vect
    functions were not strictly called by the higher level ec_encode_data() and
    needed independent testing.  As this has now changed the extra tests can be
    removed as redundant.
    
    Change-Id: I8a95e31487b150a2a8f929c5586785524d951fde
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 2988108f6ba0fa2914bcad3fa92bedcfccc3834b
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 10:32:21 2020 +0100

    releasing package libisal version 2.29.0-2

commit 6e8351f7ebfff33c6bac86386293af6090c9f392
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 10:27:23 2020 +0100

    Set DPKG_GENSYMBOLS_CHECK_LEVEL to 4.

commit eb84eb8738ea517acc0a32788a9d00019013c2a2
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 10:06:40 2020 +0100

    Update ARM symbols file.

commit 368d75a08cdfb71b33d0dbf796389eab099a60bc
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:58:06 2020 +0100

    releasing package libisal version 2.29.0-1

commit 01e597de206379be31fd3179ba043d0eeca87aa5
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:55:20 2020 +0100

    Update symbols files

commit ca490ca39741945d858efb2b5cc1aafa16a5ff54
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:53:08 2020 +0100

    Bump Standards-Version to 4.5.0 (no changes).

commit 6ac9f06ff3e77c277231cee648f7660956225d9b
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:52:47 2020 +0100

    Rules-Requires-Root: no.

commit 63ca3886421f7e30db18c7ba78b783d108f18108
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:52:34 2020 +0100

    Switch to nasm for AVX512 support.

commit 30ae11804f9aa8b69d89ff866c34491e6ad3287a
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:44:47 2020 +0100

    Update symbols files.

commit e753f085baba10a2933574b5b4358789e3571aea
Merge: 42899fb 806b55e
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:35:46 2020 +0100

    Merge tag '2.29.0' into debian/train
    
    ISA-L 2.29 release

commit 42899fbec9263259fc0e2b8882b3e9cf76450908
Author: Ondřej Nový <onovy@debian.org>
Date:   Mon Mar 2 08:35:38 2020 +0100

    New upstream release.

commit 806b55ee578efd8158962b90121a4568eb1ecb66
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Feb 26 17:40:37 2020 -0700

    build: Bump revision to 2.29
    
    Change-Id: I78cfa77864f3fd77c3b63199bc18fd1782fe3dc2
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 2db2cd557c58dcd44c5d3052e8f95655281f1c97
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Feb 26 12:04:18 2020 -0700

    Update release notes for v2.29 additions
    
    Change-Id: Id9ba5da760ee60dbb1de47162e6276f522bc0850
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 6136a04bbe47c34c11c488560b47d9955bd99494
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Feb 21 11:28:59 2020 -0700

    crc: Add new vclmul version of crc16_t10dif
    
    Change-Id: Ic068f35d5d8c34b74128b7a2ea8e82f5fa693c28
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 5ef6eb5c68704dc725db6f9e06a9c7debce745e2
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Feb 19 18:37:45 2020 -0700

    crc: Add new vclmul version of crc32_ieee
    
    Change-Id: Ib761e3240d8252ce84e9abeadb568dce60742717
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 25a673d75a53eed34cc82abfe608460a41ec0866
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Jan 29 16:47:27 2020 -0700

    crc: Add new vclmul version of gzip_refl
    
    Change-Id: I8050853dcd177f4fb506f32f5fa723f7a1d3cded
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 4217930338360cdfd2ed3e86c925937353ce24eb
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Jan 29 14:16:37 2020 -0700

    crc: Add vec version of crc16_t10dif_copy
    
    Change-Id: I5f73e8a38efd1ff50d30a39689d9d85da702e809
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 02a41e0653d774ae106c1475297ccafea93956ed
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Jan 29 13:48:40 2020 -0700

    crc: Add vec version of crc32_ieee when avx avail
    
    Change-Id: I5542ee93156c26f5a23feb89b82f4c51f282777d
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit d4131bb3d31f0b0cc1f08ba09c5c93d0bcd7cd11
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Jan 27 16:38:34 2020 -0700

    crc: Add vec version of crc32_gzip_refl when avx avail
    
    Change-Id: I4a069c318c809dcd21a6ebc47d3e0d1c131599ea
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit ad22a906867b242a67b4c36d17ca4db36965042e
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Thu Jan 23 16:53:31 2020 -0700

    crc: Add vec version of crc16 when avx available
    
    Vec versions mix much better with other avx code.
    
    Change-Id: I2544c75d09231ee70f16c384b1e57062976199d9
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 180c74aefd006073e2f6272aaef33b5c957224ed
Author: Hong Bo Peng <penghb@cn.ibm.com>
Date:   Thu Feb 20 11:47:53 2020 +0800

    enable VSX SIMD in ISA-L for ppc64le
    
      1) Implement the ErasureCode function in Altivec Intrinsics
      2) Coding style update
    
    Change-Id: I2c81d035f4083e9b011dbf3b741f628813b68606
    Thanks-to: Daniel Axtens <dja@axtens.net>
    Signed-off-by: Hong Bo Peng <penghb@cn.ibm.com>

commit a3d5cd8642d4eab99264bd6f80cd74d8b6306c8b
Author: Zhang Jinde <zjd5536@163.com>
Date:   Thu Jan 9 06:12:03 2020 +0800

    igzip: Fix clang error on dep generation
    
    Clang errors when generating dependencies due to a stray semicolon following a
    function definition.
    
    Change-Id: Iefb4aca988b643bb62a69bbbaf197aca20a2d085
    Signed-off-by: Zhang Jinde <zjd5536@163.com>

commit 163b6cd934a2ec9f255eba346e3330c49f779c31
Author: Zhang Jinde <zjd5536@163.com>
Date:   Tue Jan 7 15:33:49 2020 +0800

    igzip: Fix for deflate logic buffer management
    
    Fixes invalid logic that attempted to eliminate unnecessary copy of input to the
    history buffer in cases where it is not required. Correction should improve
    performance and not change functionality.
    
    Change-Id: Ife24dcc9d920ce220b1a394031e971321737a171
    Signed-off-by: Zhang Jinde <zjd5536@163.com>

commit fc69e8fc795a66f3a9913b62dbcbfac221307bdb
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Mon Dec 23 13:52:48 2019 +0800

    igzip: fix deflate hash bug
    
    if next_in equal end_in, the function should
    return.
    
    Change-Id: I59e631bb1f24835fd43f943a3736e016c4e2d0ac
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit e2b07bbd4492255744304dc31831598fba051fa8
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Mon Dec 16 13:31:45 2019 +0800

    build: fix debug build problem
    
    Remove strip command when lib_debug=1
    
    Change-Id: I1203fcbfefb3b87080e9ba12ccbfb8018a008147
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 936d05fc4f8762c46ab6d344900322e353b090ec
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Thu Dec 12 16:14:48 2019 +0800

    igzip:Add decode huffman code for aarch64
    
    Change-Id: If26cc4fd97b078b5f3b02e5f6f121a12ec73f671
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit ad49e580dc5a63b7575239131985854c53312639
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Dec 13 16:24:05 2019 -0700

    doc: Fix missing description of gf_matrix_inverse
    
    Doc missed issue of input matrix destruction.
    Fixes #116
    
    Change-Id: Ic840b27532d90518dd21ec2701c278a1c3b61a8b
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 2b8cc393afca46d2c72eb61a1928d204396795db
Author: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
Date:   Tue Dec 3 09:33:00 2019 +0800

    igzip: implement gen_icf_map with assembly
    
    Change-Id: I74e6200a732acfaac44b7f5a82bd4a2215ba1535
    Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>

commit f430953f0adb6c0b93a0f890ccbb66a1ec704985
Author: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
Date:   Wed Dec 4 17:14:21 2019 +0800

    igzip: cleanup perf test related code
    
    This patch addresses some cppcheck issues.
    And some minor changes to maintain code consistency.
    
    - Cleanup cppcheck issues.
      [log][igzip/igzip_perf.c] (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
      [log][igzip/igzip_hist_perf.c:132]: (error) Memory leak: outbuf
    
    - Some minor changes to maintain code consistency.
      igzip/igzip_build_hash_table_perf.c
      igzip/igzip_hist_perf.c
      igzip/igzip_semi_dyn_file_perf.c
    
    - delete unused variable
      outbuf and outbuf_size from igzip/igzip_hist_perf.c
    
    Change-Id: Icbbd8f70de689931c8a844d89e457af8d97c6793
    Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>

commit 683364c47b7e1cc336558329057de805208f1562
Author: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
Date:   Thu Nov 14 17:48:28 2019 +0800

    igzip: implement encode_deflate_icf with assembly
    
    Change-Id: I90b12da2d2a96bfdb47d29ab329648247a756585
    Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>

commit 5eeb33f69c456e95228e27733a25f828e3505c46
Author: John Kariuki <John.K.Kariuki@intel.com>
Date:   Wed Jun 12 16:09:52 2019 -0700

    ec: add AVX512 ec functions with 5 and 6 outputs
    
    Added AVX512 optimized functions to calculate the
    GF(2^8) vector dot product with 5 and 6 outputs
    at a time. Also added GF(2^8) vector multiply
    AVX512 optimized functions with 5 and 6 accumulate.
    
    Change-Id: I6d2c080f4f4f8e4823ad9a9be2c65c3b5b3bb1f8
    Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>

commit 4785428d2f31db08e629462077e95a28a1a1bbce
Author: Samuel Lee <samuel.lee@microsoft.com>
Date:   Thu Oct 10 18:15:52 2019 +0100

    crc: arm64 implementation tweaks
    
    + Utilise `pmull2` instruction in main loops of arm64 crc functions and
    avoid the need for `dup` to align multiplicands.
      + Use just 1 ASIMD register to hold both 64b p4 constants,
    appropriately aligned.
    + Interleave quadword `ldr` with `pmull{2}` to avoid unnecessary stalls
    on existing LITTLE uarch (which can only issue these instructions every
    other cycle).
    + Similarly interleave scalar instructions with ASIMD instructions to
    increase likelihood of instruction level parallelism on a variety of
    uarch.
    + Cut down on needless instructions in non-critical sections to help
    performance for small buffers.
    + Extract common instruction sequences into inner macros and moved
    them into shared header - crc_common_pmull.h
    + Use the same human readable register aliases and register allocation
    in all 4 implementations, never refer to registers without using human
    readable alias.
      + Use #defines rather than .req to allow use of same names across
    several implementations
    + Reduce tail case size from 1024B to 64B
    
    + Phrased the `eor` instructions in the main loop to more clearly show
    that we can rewrite pairs of `eor` instructions with a single `eor3`
    instruction in the presence of Armv8.2-SHA (should probably be an option
    in multibinary in future).
    
    Change-Id: I3688193ea4ad88b53cf47e5bd9a7fd5c2b4401e1
    Signed-off-by: Samuel Lee <samuel.lee@microsoft.com>

commit 0a8d05a81e51d7f209b0d7bf7b4296a0a1a471a9
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Fri Nov 1 15:01:44 2019 -0700

    doc: Move arch-dependent build instructions to readme
    
    Removed the redundant parts that apply to all arch.
    
    Change-Id: I2015c436cc8ea09913a8d0d4ce2cf1f112d71dde
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 02a86dfb3f4530509cc6248805d1eff64aaf6279
Author: Hang Li <lihang48@hisilicon.com>
Date:   Thu Oct 31 17:31:03 2019 +0800

    erasure_code: modify eor way in aarch64 neon codes
    
    Change-Id: I9fb9219c5f280ed88194ec63234af046a5a036ae
    Signed-off-by: Hang Li <lihang48@hisilicon.com>

commit ce9e56054a3b82ae954163f6ac643cff7965bad1
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Fri Oct 18 10:05:05 2019 +0800

    igzip:implement deflate hash with assembly
    
    Change-Id: I39b3a37cd291c40f597750839c27db2a6a571fe5
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 216d0f929b92112c74062d82e4ec387149b113dc
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Sat Oct 12 14:34:55 2019 +0800

    build: fix cross compile issue
    
    Replace hardcode gcc with $(CC). as_filter
    will work correct in cross compile
    
    Change-Id: I484d5074abdfc80ed5cd14fdd1358274f306bcfd
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 5d7724898dc44b5a028553bd3d63b74ebceef5c8
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Wed Oct 23 13:56:35 2019 +0800

    build: fix wrong use the register name
    
    The third parameter must be 32bit register . Those assmebly
    put 64bit register here , it is wrong .
    
    Change-Id: Iebe17516b555a6a9b94ea7baa4778ad4b9dd0878
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit b441659879ff829c11019ec7cf1bad89b8575b6a
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Mon Oct 14 16:46:26 2019 +0800

    multibinary: fix strict-prototype warning
    
    with -Wstric-prototype option , GCC report the
    warning .
    
    Change-Id: Ic2d1adb566ad21deec65c66552e2863254e1376a
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit f0104600a0a3e20732d00823565213b616d2fc80
Author: Jerry Yu <jerry.h.yu@arm.com>
Date:   Thu Oct 31 16:36:42 2019 +0800

    build: disable clang support in ci
    
    - Disable clang test for travis and drone.io
    - Add document about compiler requirement
    
    Change-Id: I81f8dc31088d40f315dd4ec062bed5df8ab7b633
    Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>

commit 6b70da5051f33693998c4427122e098b9fc1b120
Author: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
Date:   Tue Oct 22 16:14:18 2019 +0800

    igzip: implement set_long_icf_fg with assembly
    
    Change-Id: I21ac55985a56c2b7b0a684934c076600d90f8b0a
    Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>

commit 4ed944c4b1978f182995167584aef68cb61561a6
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Wed Oct 30 11:16:49 2019 -0700

    build: Fix travis osx issue with brew update
    
    Bug in Homebrew auto-update causes post-update install to use the old
    environment.
    
    Change-Id: I03e20d899f558f71579dfd4be3f96903b77f1998
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit 621cf92c529e43c04da45cd026bc4f492e90f798
Author: Hang Li <lihang48@hisilicon.com>
Date:   Sat Oct 26 13:42:24 2019 +0800

    erasure_code: modify perf benchmark loop
    
    Change-Id: Ie45ceb3ac55ab943a155e2a3f9f6b765cd94d7a1
    Signed-off-by: Hang Li <lihang48@hisilicon.com>

commit 2f9eef537ce1caac08e18a250d06b2999049d63f
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Oct 28 15:53:14 2019 -0700

    build: Fix autoconf build for mingw target
    
    Change-Id: Ie5ae17556f8cc95af8e59c8bd81a958c94455cd1
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

commit e6848434aec38b932f9d0954a099e4e4c2522d3d
Author: Greg Tucker <greg.b.tucker@intel.com>
Date:   Mon Oct 28 15:52:48 2019 -0700

    test: Fix issue keeping mingw tests from running
    
    Change-Id: I1e72ed99c2f09cbad488774313cddafdb1ce5de8
    Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>