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intel-graphics-compiler (1.0.5353.1-2) [PTS] [DDPO]

NEW: VCS has unreleased changes: 1.0.7423-1 > 1.0.5353.1-2

• Git: https://salsa.debian.org/opencl-team/intel-graphics-compiler.git
• 
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• Branch: master
• Path: debian/changelog
• Browser: https://salsa.debian.org/opencl-team/intel-graphics-compiler
• Last scan: 2021-07-30 21:17:07+00
• Next scan: 2021-08-06 12:05:00+00
• Debian changelog in Git:

  intel-graphics-compiler (1.0.7423-1) UNRELEASED; urgency=medium
  
    * New upstream release.
    * fix-ftbfs.diff: Dropped, upstream.
    * rules: Fix config option to select the llvm version.
  
   -- Timo Aaltonen <tjaalton@debian.org>  Mon, 10 May 2021 18:39:29 +0300

• This branch is 129 commits ahead of tag debian/1.0.5353.1-2
• Git log:

  commit e0b2eccb535ed783c51aeb320de441067ab13c3a
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon Jun 7 12:40:29 2021 +0300
  
      bump the version
  
  commit ff5885c639b297538f5352bd34376e0e530c249b
  Merge: 242b37e7 3104b45b
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon Jun 7 12:39:18 2021 +0300
  
      Merge branch 'upstream'
  
  commit 3104b45be5ed35a7f6a8d52ff4a7f339f582e055
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Wed May 12 07:49:11 2021 +0000
  
      Update the insertInstLabel to fixEndifWhileLabels
  
  commit 708bc5f58df255bfb4aed73408d6f1f552a50cb4
  Author: Aleksander Us <aleksander.us@intel.com>
  Date:   Tue May 11 14:35:33 2021 +0000
  
      Pass llvm options using compilation options
      
      Move llvm options parsing into backend compilation phase to make
      things more explicit.
  
  commit 98e521bc61a868c29120a63327b4a0e8a2fa6c22
  Author: Jhanani Thiagarajan <jhanani.thiagarajan@intel.com>
  Date:   Tue May 11 20:48:37 2021 +0000
  
      Expanding BufferType
      Buffer Type range is set to 32 instead of 16.
  
  commit a70235e451489e2322e0cee5e758cdce152fcab2
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Mon May 10 08:24:37 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 81b88fa03977f140b3eafb480774c0149fceaa42
      Fix an incorrect condition when deciding if an unreferenced dcl can be
      removed from list.
  
  commit 43b04c130e2340f6d42e53bb09eb84866dd78483
  Author: Dmitry Kostin <dmitry.kostin@intel.com>
  Date:   Tue May 11 20:27:33 2021 +0000
  
      Sync change
  
  commit fd980e30baccf7b8e78274ea72ac0a5266fbecc6
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Tue May 11 18:37:28 2021 +0000
  
      Fix the bug in flag register spill/fill clean up
  
  commit b091f925f058b497453b392446f15e0116f598ab
  Author: Dmitry Kostin <dmitry.kostin@intel.com>
  Date:   Sun May 9 23:03:04 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 1af3fb3e3cca9222416fd05b394b053736dd0052
      Sync change
  
  commit 7de920040340e593388b8d547102328738e6b44f
  Author: Hou-Jen Ko <hou-jen.ko@intel.com>
  Date:   Mon May 10 19:34:51 2021 +0000
  
      [IGC feature][CodePatch] Enable ZWDelta in Code Patch
  
  commit 8260a62e55093b9b15283303a0950d42707d1cce
  Author: Aleksander Us <aleksander.us@intel.com>
  Date:   Tue May 11 12:30:55 2021 +0000
  
      Remove debug llvm options parsing in VC
      
      The same effect can be achieved with IGC_VCInternalOptions and
      -llvm-options internal option.
  
  commit 5b7561a3fa04a9f0e3c985a60ddafc687fd44474
  Author: Aleksander Us <aleksander.us@intel.com>
  Date:   Fri May 7 10:52:10 2021 +0000
  
      Add missing library for vc codegen
  
  commit 59813259de42ea8551aea4ecb7be589899936324
  Author: Filipkowski, Lukasz <lukasz.filipkowski@intel.com>
  Date:   Tue May 11 07:17:38 2021 +0000
  
      Minor source code refactoring: move FixAddressSpaceInAllUses() to helper file.
      Private memory resolution minor refactoring: convert int64 directly to pointer to allocated type.
  
  commit 245ef55318812f5a165a0d127f5b26981676b60c
  Author: Anatoly Parshintsev <anatoly.parshintsev@intel.com>
  Date:   Sun May 9 05:55:37 2021 +0000
  
      cleanup old emulation functions to preserve compatibility with old ISPC
  
  commit 40a982e2af9679053d1123d8769b241a482c2dc5
  Author: Maciej Kalinski <maciej.kalinski@intel.com>
  Date:   Mon May 10 13:52:46 2021 +0000
  
      Trivial refactoring.
  
  commit 81b88fa03977f140b3eafb480774c0149fceaa42
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Mon May 10 08:24:37 2021 +0000
  
      Fix an incorrect condition when deciding if an unreferenced dcl can be
      removed from list.
  
  commit 64a79bc2b9435fb42ad12d60c6bf695506e2f150
  Author: Wei Chen <weiyu.chen@intel.com>
  Date:   Tue May 11 00:10:01 2021 +0000
  
      Detect local to generic pointer casts, second try.
  
  commit 332f230accd4ab405f0f6862d1dfaefb46db8f0a
  Author: Gang Y Chen <gang.y.chen@intel.com>
  Date:   Sat May 8 15:59:36 2021 +0000
  
      Need to check Bti Value is constant first
  
  commit 364808d979a096b353637fb4dad3f5064068982b
  Author: Gu, Junjie <junjie.gu@intel.com>
  Date:   Mon May 10 20:37:46 2021 +0000
  
      Minor improvement to TGL workaround
  
  commit aa3f43847078d5a991177739a54e4034ee5bbf52
  Author: lgotszal <lukasz.gotszald@intel.com>
  Date:   Wed May 5 16:20:19 2021 +0000
  
      update copyright headers in IGC ZEBinWriter
  
  commit a6671789e2f05d0fa55019aea40b1e05fed99b3e
  Author: Diana Chen <po-yu.chen@intel.com>
  Date:   Fri May 7 23:37:50 2021 +0000
  
      ZEBinary: support Rela format in ZEELFObjectBuilder
  
  commit 8e1ed2cff476b2ecfc1a45242bd27bfc6cd2687d
  Author: Irene Wu <irene.w.wu@intel.com>
  Date:   Fri May 7 20:14:21 2021 +0000
  
      Fix the optimization EnableMergeTransposeSLM
  
  commit 905c6bec14f61afbee516a063d5d4ac0c1debd90
  Author: lgotszal <lukasz.gotszald@intel.com>
  Date:   Wed May 5 10:54:04 2021 +0000
  
      update copyright headers in IGC Options
  
  commit 242b37e7721bee62e3c0ea009ab87b416cb291e1
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon May 10 20:26:51 2021 +0300
  
      bump the version
  
  commit 1ec3533b728e16ae1e493cab21c5d3095029e43b
  Merge: 5799f69f 95220438
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon May 10 20:26:21 2021 +0300
  
      Merge branch 'upstream'
  
  commit 5799f69f619cdb94b10ebc83c9ee4746ceb046cd
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon May 10 20:25:00 2021 +0300
  
      rules: Fix config option to select the llvm version.
  
  commit 75aca49d0c1896e0f17d47d95ccc5d020980011d
  Author: lgotszal <lukasz.gotszald@intel.com>
  Date:   Wed May 5 08:34:23 2021 +0000
  
      update copyright headers in IGC AdaptorCommon
  
  commit cbbff952c272870f1c6e35b69496da3adf894b97
  Author: lgotszal <lukasz.gotszald@intel.com>
  Date:   Thu Apr 29 20:48:01 2021 +0000
  
      update copyright headers in IGC AdaptorOCL
  
  commit 96aa7c52e17fe305f3777edf3072e94c28eb1acf
  Author: Scott Pillow <scott.pillow@intel.com>
  Date:   Sun May 9 02:08:01 2021 +0000
  
      Revert unrolling threshold change.
  
  commit 50c4b5c7d6a4f3cf49cd4a9ae3d81457286f5285
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon May 10 18:43:24 2021 +0300
  
      fix-ftbfs.diff: Dropped, upstream.
  
  commit 7bf65c01e7542185fe7ca9389d370003468cb2f9
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon May 10 18:40:46 2021 +0300
  
      bump the version
  
  commit fcd1e1cabd230a76f4cc960164d500c061d23c16
  Merge: 15ace448 8b823ff1
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon May 10 18:24:45 2021 +0300
  
      Merge remote-tracking branch 'origin/master' into m
  
  commit 15ace44814174d9326bb29a66a00335af42d0e80
  Merge: e644ad61 a4af189e
  Author: Timo Aaltonen <tjaalton@debian.org>
  Date:   Mon May 10 18:24:37 2021 +0300
  
      Merge tag 'igc-1.0.5353.1' into m
  
  commit a2f6aff9877f89e8169c4434d072c6ab3296d313
  Author: Andrzej Ratajewski <andrzej.ratajewski@intel.com>
  Date:   Mon May 10 08:24:37 2021 +0000
  
      Transform SPV_INTEL_optimization_hints into SPV_KHR_expect_assume
  
  commit 1a212cc1dd68a83144d4c66d68f9cd3a1e6c0f0a
  Author: Maciej Kalinski <maciej.kalinski@intel.com>
  Date:   Thu May 6 23:36:45 2021 +0000
  
      Refactoring
  
  commit c5182e4695017831105dc6a268051730efa8c12b
  Author: Krystian Andrzejewski <krystian.andrzejewski@intel.com>
  Date:   Fri May 7 15:57:34 2021 +0000
  
      Dump just after each pass execution
  
  commit 768c1890030c0cc0250a48709dc1bef1c3646a95
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Mon May 10 08:58:03 2021 +0000
  
      Minor improvements to split aligned scalar pass.
  
  commit 05e9538d0276028c20887094e29cd15b83ac59b7
  Author: Jurek, Pawel <pawel.jurek@intel.com>
  Date:   Fri May 7 12:38:51 2021 +0000
  
      Workaround for __IMAGE_SUPPORT__ macro definition in Clang.
      
      Clang always defines __IMAGE_SUPPORT__ macro for SPIR target. It seems this is not compliant with OpenCL spec.
  
  commit 1af3fb3e3cca9222416fd05b394b053736dd0052
  Author: Dmitry Kostin <dmitry.kostin@intel.com>
  Date:   Sun May 9 23:03:04 2021 +0000
  
      Sync change
  
  commit 8eb9254ec05851224e9e083df0550bc4354a4c78
  Author: Wei Chen <weiyu.chen@intel.com>
  Date:   Fri May 7 22:32:30 2021 +0000
  
      Fix packed immediate handling on platforms that don't have byte regioning.
  
  commit 80368cea6c89e6e38140254968898de5c1315551
  Author: Szymichowski, Pawel <pawel.szymichowski@intel.com>
  Date:   Thu May 6 17:53:30 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 39cc2b4e181a51c819c6e839ffc0b56246cc84f3
      Moved destroyDummyFunc() back to ~ScalarizeFunction()
      due to functional regression
  
  commit 865b3b6e02fd99fea1bc8adeee9e16ae55f5543e
  Author: Gu, Junjie <junjie.gu@intel.com>
  Date:   Thu May 6 01:05:06 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 0de60dc38ce4c2a270c4d285c81056e5b59f975a
      Minor improvement to TGL workaround
  
  commit 4b90dabeb677b89f83d54e5c9387a8ef27567cc4
  Author: Gu, Junjie <junjie.gu@intel.com>
  Date:   Fri May 7 19:34:29 2021 +0000
  
      Improve jump codegen by setting uniform if jump's flag is workgroup/global uniform
      under EU fusion.
      
      It is off for now. And it can be turned on by setting key EnableWorkGroupUniformGoto to 1.
  
  commit 7f5caaf3202d4c944ac77776389a537308e917a7
  Author: Lukasz Wesierski <lukasz.wesierski@intel.com>
  Date:   Fri May 7 13:34:07 2021 +0000
  
      Correction in LLD build
  
  commit 14491a6478cc68121a063e6189aa3d864dc753b0
  Author: Gang Y Chen <gang.y.chen@intel.com>
  Date:   Wed May 5 14:52:31 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 82530e00a80b7065b89182d37557e6299acdb85e
      Insert a custom intrinsic to indicate vector
      is uniform after promotion. For GPGPU case, I try
      to Make it more precise by inserting at the common
      dominator of all loads and stores.
  
  commit ffde5573ab62728ac7cca2173220fd2a57e882d9
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Fri May 7 17:41:37 2021 +0000
  
       fix CSEL before EOT, there may be atomic URB inst
  
  commit 2a76dc47b505227a8372b2f006fd922fc54f89c6
  Author: Hou-Jen Ko <hou-jen.ko@intel.com>
  Date:   Fri May 7 05:34:43 2021 +0000
  
      [IGC bugfix][CodePatch] pre-allocate all R1Lo aliases
  
  commit a1686480ca604e463db1d96143c822bbb910e689
  Author: sys-igc <IGC@intel.com>
  Date:   Fri May 7 15:11:40 2021 +0000
  
      Changes in code.
  
  commit 541bad27fca64b9d50d2969e77050b05dbe7bf18
  Author: dkostin <dmitry.kostin@intel.com>
  Date:   Fri May 7 08:02:57 2021 +0000
  
      Changes in code.
  
  commit b061d7ae1fa2bf73554c3cc097c59de330289397
  Author: Burke, Devan <devan.burke@intel.com>
  Date:   Tue May 4 16:29:26 2021 +0000
  
      Flip DispatchAlongY override setting to reflect new default.
  
  commit e78d149954b339ac9f21052b5c17e1625e55da8a
  Author: Krystian Andrzejewski <krystian.andrzejewski@intel.com>
  Date:   Wed Apr 28 08:23:34 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 6893d21f783c13ef206323761ecad991b02ffe2d
      Dump just after each pass execution
  
  commit a67911b894a90536ef7af526708e4b30d41e2679
  Author: Andrzej Ratajewski <andrzej.ratajewski@intel.com>
  Date:   Fri May 7 10:23:22 2021 +0000
  
      Implement more efficient emulation for floating point global atomics
  
  commit 02423473bf21245be6267687ab205bf15904d272
  Author: Piotr Jarosz <piotr.jarosz@intel.com>
  Date:   Thu May 6 18:09:48 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: cad551848a01c1f066a0dc7d2ad1726b21053121
      The LopPrecisionOpt does not support scalars
      and vectors of less than 4 elements.
      This change adds support these data types.
  
  commit b321cb8bef1ed9fff0bd9cec51a5ab0d232fc908
  Author: Szymichowski, Pawel <pawel.szymichowski@intel.com>
  Date:   Fri May 7 08:52:39 2021 +0000
  
      Refactored Scalarizer pass:
      * add created dummy functions to the current module so they can be properly
      removed; previously whey were hanging without parent
  
  commit 6ffcd05cf2749b17d7b1b95fd3e34077e43dbbaa
  Author: Aleksander Us <aleksander.us@intel.com>
  Date:   Thu May 6 20:07:06 2021 +0000
  
      Refactor option parser
      
      Split single file into separate: main file with definitions and
      separate file for vc options. Add helper definitions into main file.
  
  commit e062402217e1ad81c6ffbc88a5d08e37163556dd
  Author: Anatoly Parshintsev <anatoly.parshintsev@intel.com>
  Date:   Thu May 6 14:44:00 2021 +0000
  
      cosmetic fixes for VC emu boilerplate generator
  
  commit 14f09a51a516382e9f659ce22cac28f8e4ff3396
  Author: pratikashar <pratik.j.ashar@intel.com>
  Date:   Thu May 6 09:32:29 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 4e936c245bcbc799bd580d8fdfd75981dbd06aec
      Internal change.
  
  commit e016b799e90a86bbcf919836583e27c7ae318593
  Author: Sergei Kachkov <sergei.kachkov@intel.com>
  Date:   Fri May 7 07:41:00 2021 +0000
  
       Do not load zero values from genx.alloca
  
  commit f57f9d4763b8718021db36c4fd5dc543392157f7
  Author: Marcin Naczk <marcin.naczk@intel.com>
  Date:   Thu May 6 07:36:11 2021 +0000
  
      Fix Travis environmental error, libc6
  
  commit 952204388d06801606b9cd2954362ac3d17ee19a
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Wed Apr 21 12:28:33 2021 +0000
  
      Add comment.
  
  commit 6b0689dad6910ec6e5bba8fa3c3ac071ee0333d8
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Wed Apr 21 09:34:22 2021 +0000
  
      Avoid O(n^2) iteration over kernel declares.
  
  commit 562c0d592eb81dec136113d5b5c25333a35bc9ba
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Wed Apr 21 23:41:40 2021 +0000
  
      Disable bundle conflict reduction if there is spill
  
  commit 22fdd0421538a4b1dca2d9607dce8c720d947e4a
  Author: liufang <fang.l.liu@intel.com>
  Date:   Tue Apr 20 21:39:09 2021 +0000
  
      Minor change
  
  commit aa9b3c74edf363bfb42efa542f9e601a794bf5e0
  Author: David Woo <david.j.woo@intel.com>
  Date:   Wed Apr 21 18:15:35 2021 +0000
  
      Refactoring
  
  commit 670eeba89ec142263819637f14ca2e2c07fcc896
  Author: Gang Y Chen <gang.y.chen@intel.com>
  Date:   Wed Apr 21 02:55:57 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 4f18eca120c62f74dc2c6b1d862266240d2d2913
      Insert VectorUniform at the nearest dominator of all stores
  
  commit 3548445f96cfa757061629dc49bf4df3a8904271
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Wed Apr 14 05:44:58 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 32af7f7c36d24f4f6aa5f90b2fa7237eba5c2c46
      Enable split scalar pass.
  
  commit 291667eb01e3ba38a04ba12646aed638f76e7972
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Wed Apr 21 05:22:41 2021 +0000
  
      Change the footprint for OWORD load.
  
  commit 24a0eac3df1189d1f8053a8bfdaaceddebfbdf37
  Author: Viacheslav Rybalov <viacheslav.g.rybalov@intel.com>
  Date:   Fri Apr 16 01:02:14 2021 +0000
  
      Add check for IGC destruction.
      If IGC static objects are destructed then
      IGC returns error code to driver.
  
  commit e1cf4f577d8a5d067c89a1e96a26b1f30e7cf117
  Author: Aleksander Us <aleksander.us@intel.com>
  Date:   Tue Apr 20 21:52:03 2021 +0000
  
      Copy clang sources to handle opencl-clang patching
  
  commit 4f18eca120c62f74dc2c6b1d862266240d2d2913
  Author: Gang Y Chen <gang.y.chen@intel.com>
  Date:   Wed Apr 21 02:55:57 2021 +0000
  
      Insert VectorUniform at the nearest dominator of all stores
  
  commit 4bc6b443a545706b384b750533b5838c1d7251c1
  Author: Zoltán Böszörményi <zboszor@pr.hu>
  Date:   Wed Apr 21 09:07:19 2021 +0000
  
      Fix build with LLVM 12
      
      Removed TargetLibraryInfo.h include from AddressSpaceAliasAnalysis.cpp as this was causing treat-warning-as-error buildbreak,
      Added casts to fix warnings,
      Replaced ConstantPropagation and IPConstantPropagation passes with IPSCCP passes,
      reasoning here: https://lists.llvm.org/pipermail/llvm-dev/2020-July/143788.html
      
      Original pull-request: https://github.com/intel/intel-graphics-compiler/pull/171
      
      Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
      Co-authored-by: Pawel Szymichowski <pawel.szymichowski@intel.com>
  
  commit 7d73b048e62210cfa8e6b9cf479f559e2ccf3d79
  Author: Andrzej Ratajewski <andrzej.ratajewski@intel.com>
  Date:   Wed Apr 21 11:35:47 2021 +0000
  
      Respect per instruction contraction flag in mad pattern match.
      
      SPV_INTEL_fp_fast_math_mode introduces AllowContractFastINTEL fast math flag. When instruction is decorated with this flag, contractions are allowed even if it may violate language standard. This enum maps to LLVM fast math flags, but was not respected in "mad" instruction pattern match.
  
  commit 34f4fb072c2a0f70046c521239705bb5a13bd34e
  Author: Aleksander Us <aleksander.us@intel.com>
  Date:   Thu Apr 15 15:17:37 2021 +0000
  
      Add warning when -cmc option is used for SPIRV path
  
  commit e0e9d0b194f4695dcf16a49f4a8766c035386772
  Author: Piotr Fusik <piotr.fusik@intel.com>
  Date:   Tue Apr 20 15:33:01 2021 +0000
  
      Refactor RegAlloc
  
  commit c79564dcd537eda8bd642dad7aced1180eb43987
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Tue Apr 20 22:08:39 2021 +0000
  
      Add BCR support in RA for TGL
  
  commit a52cc6dbdc669d8efb33668de39d5ce2b417bfc8
  Author: lgotszal <lukasz.gotszald@intel.com>
  Date:   Wed Apr 7 16:58:08 2021 +0000
  
      refactor asserts in GenXVectorDecomposer.cpp
      no functional change
  
  commit 95fa8d37a600b245f3deae5be5390402b37e36c2
  Author: lgotszal <lukasz.gotszald@intel.com>
  Date:   Wed Mar 17 13:21:38 2021 +0000
  
      refactor asserts in GenXTidyControlFlow.cpp
      no functional change
  
  commit 32af7f7c36d24f4f6aa5f90b2fa7237eba5c2c46
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Wed Apr 14 05:44:58 2021 +0000
  
      Enable split scalar pass.
  
  commit 14656ecf1705029db26899c5516837b3ffcff750
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Sat Apr 17 20:34:53 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 713ea89c396d19188c4f4ac5786ea87e4b8dce5a
      Experiement for flag register SWSB
  
  commit 1a4fc87f5b46297c5641545326c23d69116611d8
  Author: Tim Bauer <timothy.r.bauer@intel.com>
  Date:   Tue Apr 20 18:39:16 2021 +0000
  
      Backout G4IR retry #1
  
  commit cb8025412ee77e752d7f1f285d9e7010df3767f5
  Author: Harshad Untwale <harshad.untwale@intel.com>
  Date:   Mon Apr 19 22:36:22 2021 +0000
  
      Enable Shader debug hash code on for dx and ogl adapters by default
  
  commit 02846de387cd55e406819248112a7d6b8053cf83
  Author: Gu, Junjie <junjie.gu@intel.com>
  Date:   Tue Apr 20 16:49:55 2021 +0000
  
      Emulation inliner means to inline emulation functions only.
      As original functions may have alwaysinline attribute set, make sure
      the alwaysinline attr is removed before doing alwaysinline for
      emulation functions.
  
  commit 713ea89c396d19188c4f4ac5786ea87e4b8dce5a
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Sat Apr 17 20:34:53 2021 +0000
  
      Experiement for flag register SWSB
  
  commit 3f4822fbbf0159d13a51041fa6b904395e23d6af
  Author: Scott Pillow <scott.pillow@intel.com>
  Date:   Tue Apr 20 10:58:45 2021 +0000
  
      Use bit based macros.
  
  commit 0783a9d60cf83a74abd917e6cfe08f028614747b
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Tue Apr 20 00:19:24 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: ef2ad4e0aed0e4f7b65e0703c4589506c8e8c0d8
      Add BCR support for global RA
  
  commit 9cf54086188a0f55b178864791a9f846715f3884
  Author: Konstantin Vladimirov <konstantin.vladimirov@intel.com>
  Date:   Tue Apr 20 10:45:56 2021 +0000
  
      Fix CM FE Interface
  
  commit 998b373aa6e69ff8225202722389ae551ee37f1d
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Tue Apr 20 09:39:50 2021 +0000
  
      Instructions using acc operands are not candidates for this optimization
      as such instructions have alignment restrictions. Handle instances where
      topdcl is a scalar but it has aliases defining parts, eg :uq defined
      using 2 :ud.
  
  commit 21ad6a90d4706dd72f590d15da5d1647fcb5a91a
  Author: Tim Bauer <timothy.r.bauer@intel.com>
  Date:   Tue Apr 20 04:56:18 2021 +0000
  
      High-Level Load/Store G4IR support.
      The goal is to move us away from twiddling bits in descriptors every time we need to examine or modify send messages.
      * All send descriptors (formerly G4_SendMsgDescriptor) are subclasses of G4_SendDesc
      * The old raw descriptor is G4_SendDescRaw and there is a new G4_SendDescLdSt which is unused at the moment.
      * Anywhere possible, we now use the generic methods of the superclass G4_SendDesc.
      * In cases where the old code fiddles with bits directly and requires the raw descriptor, we add a type check and convert to G4_SendDescRaw (assert on fail / return false on pattern match if safe to do so (e.g. SendFusion::canFuse(..))).
      * Do not let the old raw descriptor gunk pollute the generic interface of the parent.
      * retry #2 of reverted ci-comp_igc-10352/#19876 (fixed defect with G4_InstSend::canBeEot())
  
  commit e644ad61a1e8d9191dbabaca85f9fffc90a3d4bb
  Author: Warumzer, Jakub <jakub.warumzer@intel.com>
  Date:   Tue Apr 20 07:06:59 2021 +0000
  
      Sync change
  
  commit 4d97b3f89b650c7a97ab8e533f375c9d514c39c3
  Author: Anton Zabaznov <anton.zabaznov@intel.com>
  Date:   Mon Apr 19 16:31:58 2021 +0000
  
      Proper cleanup after matching reverse sqrt
  
  commit ef2ad4e0aed0e4f7b65e0703c4589506c8e8c0d8
  Author: bcheng0127 <bu.qi.cheng@intel.com>
  Date:   Tue Apr 20 00:19:24 2021 +0000
  
      Add BCR support for global RA
  
  commit fdabae1bf8f7e294b297ead39b5d28c0b3c16f66
  Author: Anatoly Parshintsev <anatoly.parshintsev@intel.com>
  Date:   Fri Apr 16 09:17:15 2021 +0000
  
      sanitization workarounds for VC debug
  
  commit 04921ef3b57b4ad9ba9763cea97dccef57845f9c
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Mon Apr 19 11:45:45 2021 +0000
  
      Set return location register to DW_CFA_undefined in kernel frame.
  
  commit 65224e0bee1c4c3499b974c963b03e9bfd564546
  Author: Tim Bauer <timothy.r.bauer@intel.com>
  Date:   Wed Apr 14 21:09:27 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: 1236f59a647d1fe22a5e4f375fb192ba3f33b2b9
      High-Level Load/Store G4IR support.
      The goal is to move us away from twiddling bits in descriptors every time we need to examine or modify send messages.
      * All send descriptors (formerly G4_SendMsgDescriptor) are subclasses of G4_SendDesc
      * The old raw descriptor is G4_SendDescRaw and there is a new G4_SendDescLdSt which is unused at the moment.
      * Anywhere possible, we now use the generic methods of the superclass G4_SendDesc.
      * In cases where the old code fiddles with bits directly and requires the raw descriptor, we add a type check and convert to G4_SendDescRaw (assert on fail / return false on pattern match if safe to do so (e.g. SendFusion::canFuse(..))).
      * Do not let the old raw descriptor gunk pollute the generic interface of the parent.
      * Push #5
  
  commit 1236f59a647d1fe22a5e4f375fb192ba3f33b2b9
  Author: Tim Bauer <timothy.r.bauer@intel.com>
  Date:   Wed Apr 14 21:09:27 2021 +0000
  
      High-Level Load/Store G4IR support.
      The goal is to move us away from twiddling bits in descriptors every time we need to examine or modify send messages.
      * All send descriptors (formerly G4_SendMsgDescriptor) are subclasses of G4_SendDesc
      * The old raw descriptor is G4_SendDescRaw and there is a new G4_SendDescLdSt which is unused at the moment.
      * Anywhere possible, we now use the generic methods of the superclass G4_SendDesc.
      * In cases where the old code fiddles with bits directly and requires the raw descriptor, we add a type check and convert to G4_SendDescRaw (assert on fail / return false on pattern match if safe to do so (e.g. SendFusion::canFuse(..))).
      * Do not let the old raw descriptor gunk pollute the generic interface of the parent.
      * Push #5
  
  commit c5c21e1a788cf1ef8b21fa42e1347fb8b0961cf6
  Author: Marcin Naczk <marcin.naczk@intel.com>
  Date:   Mon Apr 19 16:33:49 2021 +0000
  
      Limit Vec Element in ShaderDump
  
  commit bc9a4674d50dda88cdc94e792fab0599f5eaeb4c
  Author: Piotr Kira <piotr.kira@intel.com>
  Date:   Wed Apr 14 17:10:12 2021 +0000
  
      Check if value stored at BLOCK_INDEX_INVOKR_FUNC is NULL
      FixAddressSpace for PHINode
  
  commit ea5ab51eccdb4c9e2b2f2a41d54e9350a654aace
  Author: Piotr Kurek <piotr.kurek@intel.com>
  Date:   Sun Apr 18 15:20:30 2021 +0000
  
      Member initialization, asserts.
  
  commit 5e7e7f77218d350c7a23ffe6665e163144ba163f
  Author: Pratik J Ashar <pratik.j.ashar@intel.com>
  Date:   Mon Apr 19 07:13:28 2021 +0000
  
      Remove unnecessary legacy code that was creating lot of strings in
      dwarf.
  
  commit 51a1410122bb3309ca78224991c8c7f69da7913f
  Author: Anton Zabaznov <anton.zabaznov@intel.com>
  Date:   Thu Apr 15 16:39:30 2021 -0700
  
      [Autobackout][FuncReg]Revert of change: fb5308f33fdf2d53a78f3395b454865334d883cf
      Bale-in IntToPtr and PtrToInt operands

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